The present application claims priority to Japanese Application No. P11-175354 filed June 22, 1999 which application is incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices and in particular to a method for fabricating semiconductor devices having misalignment of the mask in mind.
2. Description of the Related Art
As the design rule for LSIs becomes microscopic, not only microfabrication of width of gate electrodes of MOS transistors but also microfabrication of spaces between the gate electrodes to reduce the size of memory cells or so become very important. This inevitably demands the microstructure of an inter-wiring pitch of metal wirings interconnecting the MOS transistors. In the conventional devices, as shown in FIG. 6A, a contact hole 402 for interconnecting an upper wiring (not shown) and a lower wiring 401 is generally formed in a portion having so-called alignment margin 403 which is provided to the lower wiring 401 to prevent the contact hole 402 from being failed in landing. A minimum inter-wiring pitch xe2x80x9cdxe2x80x9d is thus limited by a space between portions having alignment margins 403, and as a result, an inter-wiring pitch xe2x80x9cpnxe2x80x9d between portions having no alignment margin has to be wider than the minimum inter-wiring pitch xe2x80x9cdxe2x80x9d just by such margins.
In recent LSIs, it, however, becomes tight to provide such alignment margin to the lower wiring as the design rule becomes microscopic. Thus, as shown in FIG. 6B, a wiring structure in which a contact hole 412 is formed on a lower wiring 411 while scarcely reserving an alignment margin 413 is proposed.
Next, a conventional method for fabricating a multi-layered wiring for a semiconductor device will be described referring to FIGS. 7A to 7H. Assuming that devices such as MOS transistors, resistors, capacitors or the like are already fabricated, the description will start from a step for forming the first metal wiring in the multi-layered wiring process.
As shown in FIG. 7A, after fabricating MOS transistors and other devices in the lowermost layer of a silicon substrate (not shown), an interlayer insulating film 101 made of silicon oxide is formed by, for example, CVD (chemical vapor deposition) process, and the surface of which is then made flat by reflow, etchback or CMP (chemical mechanical polishing) process. A contact hole (not shown) used for making contact with the silicon substrate (not shown) is then formed in the interlayer insulating film 101. On such interlayer insulating film 101, a first conductive film (e.g., aluminum film) 121 is then formed typically in a thickness of about 500 nm. Further thereon, an insulating film 122 of a silicon oxide-base is formed typically in a thickness of about 150 nm by, for example, CVD process.
A resist mask (not shown) used for forming first wirings is then formed on the insulating film 122 by the general procedures of resist coating and lithography. The insulating film 122 and the first conductive film 121 are then etched using the resist mask as an etching mask, thereby to obtain the first wirings 102 comprising the patterned first conductive film 121 and insulating film 122 stacked thereon, as shown in FIG. 7B.
Next, as shown in FIG. 7C, an interlayer insulating film 103 made of silicon oxide is formed on the interlayer insulating film 101 so as to cover the first wirings 102 by CVD process. Using a high-density plasma CVD process in the film forming will result in an excellent inter-wiring deposition property of the interlayer insulating film 103. The surface of the interlayer insulating film 103 is then polished by, for example, CMP process, thereby to make the surface of which flat as shown in FIG. 7D.
With reference now to FIG. 7E, a resist mask (not shown) used for forming contact holes 104 to be connected to the predetermined first wirings 102 is formed on the interlayer insulating film 103. Using such resist mask as an etching mask, the interlayer insulating film 103 and the insulating film 122 are etched to form the contact holes 104 which reach to the first wirings 102. Since the interlayer insulating film 103 may in some cases have global level difference or non-uniform thickness lot by lot or wafer by wafer, over-etching is performed in the above etching so as to ensure that all of the contact holes 104 can reach the first wiring 102.
Next, as shown in FIG. 7F, a barrier metal layer (not shown) typically comprising a titanium film and a titanium nitride film stacked thereon is formed on the inner surface of the contact holes 104. The barrier metal layer ensures adhesiveness to the first wirings 102 and suppresses resistivity. A tungsten film is then formed by the CVD process so as to fill the contact holes 104. Excessive portions of the tungsten film and the barrier metal layer spreading over the top surface of the interlayer insulating film 103 are then removed by the etchback process or CMP, thereby to leave, as plugs 105, the tungsten film and barrier metal layer only in the contact holes 104.
Next, as shown in FIG. 7G, a second conductive film (for example, an aluminum film) 124 is formed typically in a thickness of 500 nm on the interlayer insulating film 103 so as to cover the plugs 105. A silicon oxide-base insulating film 125 is further formed thereon in a thickness of, for example, 150 nm.
A resist mask (not shown) used for forming second wirings is formed on the insulating film 125 by the general procedures of resist coating and lithography. The insulating film 125 and the second conductive film 124 are then etched using the resist mask as an etching mask, thereby to obtain the second wirings 106 comprising the patterned second conductive film 124 and insulating film 125 stacked thereon, and contacting the plugs 105.
Further stacking of upper wirings can be achieved by repeating the foregoing fabrication processes of the interlayer insulating film, contact holes, plugs and wirings explained referring to FIGS. 7C to 7H.
In such process, providing a reduced or no alignment margin will, however, raises problems described hereafter. Such problems will be explained referring to FIG. 8 which shows an exemplary structure having no alignment margin. FIG. 8 shows a multi-layered wiring structure having three layers of wiring fabricated as explained above in the Related Art. In this figure, device structures such as MOS transistors, resistors and capacitors fabricated in a layer lower than the multi-layered wiring structure are not shown for simplicity, whereas only the multi-layered wiring structure is shown.
As shown in FIG. 8, the first wirings 102 are formed on the interlayer insulating film 101. Thus formed first wirings 102 are capped with the silicon oxide-base insulating film 122, and further the interlayer insulating film 103 is formed so as to cover the silicon oxide-base insulating film 122. The interlayer insulating film 103 has, as formed therein, the contact holes 104 which reach to the first wirings 102, and the plugs 105 are formed in the contact holes 104. On the interlayer insulating film 103, the second wirings 106 are formed as capped with the silicon oxide-base insulating film 125, and some of the second wirings 106 are connected to the plugs 105.
On the interlayer insulating film 103, the interlayer insulating film 107 is further formed so as to cover the second wirings 106. The interlayer insulating film 107 has, as formed therein, contact holes 108 which reach the second wirings 106, and the plugs 109 are formed in the contact holes 108. On the interlayer insulating film 107, third wirings 110 are formed as capped with the silicon oxide-base insulating film 126, which are connected to the plugs 109.
If misalignment of a photomask in an exposure step for forming the contact holes 108 should occur in a process for fabricating such multi-layered wiring structure, the contact holes 108 will fail in correctly landing on the second wirings 106. Making matters worse, the second wirings 106 have no alignment margin, and the whole portion of interlayer insulating films 107, 103 are made of a silicon oxide-base material only, so that the etching for fabricating contact holes 108 tends to proceed excessively in the area not overlapped with the second wirings, and in the worst case, the contact holes 108 are formed so as to even reach the first wirings 103 as shown in the figure. If the plugs 109 are formed in such-fabricated contact holes 108, not only the third wirings 110 and second wirings 106, but also the first wirings 103 provided in the lower layer are connected each other via the plugs 109, which results in short circuit. This significantly ruins reliability of the wirings.
To solve the foregoing problem, it is therefore an object of the present invention to provide a method for fabricating semiconductor devices comprising a step for forming on a first insulating film, having a conductive body exposed thereon, a second insulating film so as to cover the conductive body, and a step for forming by etching a recess to the second insulating film so as to reach the conductive body, is characterized in that at least the lower portion of the second insulating film is formed with a material showing a faster etching rate over at least the upper portion of the first insulating film.
According to such method for fabricating semiconductor devices, at least the lower portion of the second insulating film is formed with a material showing a faster etching rate over at least the upper portion of the first insulating film, so that the etching of the second insulating film, such that for fabricating the recess so as to reach the first conductive body, will stop with certainty on the first insulating film. At least the etching should not proceed so as to penetrate the first insulating film. Thus the recess should not be formed so as to penetrate the first insulating film due to over-etching, even when misalignment of a photomask should occur and the recess cannot be formed in a predetermined position, or more specifically, even when the recess should be formed so as to be partially shifted from the position of the conductive body. Thus the recess will have its bottom on the surface of the first insulating film, or at most within the upper portion of the first insulating film. Thus the multi-layered wiring with an advanced reliability can be obtained without causing short circuit between the upper and lower wirings, which results in improved reliability of semiconductor devices.